System-on-Chip Field-Programmable Gate Arrays (SoC FPGAs) are semiconductor devices that seamlessly merge programmable logic with dedicated processor cores, often sourced from Arm. This design architecture combines the user-friendly programmability of a processor with the versatile and high-performance characteristics of a programmable logic fabric.
The embedded industry is witnessing a growing demand for processor architectures based on the open-source RISC-V, but there are limited choices for commercially available silicon or hardware. To address this gap and facilitate innovation, a company has introduced the PolarFire SoC Discovery Kit. This development kit, designed to be user-friendly and feature-rich for embedded processing and compute acceleration, aims to make cutting-edge technology more accessible to engineers of various skill levels. The open-source kit includes a quad-core RISC-V application-class processor that supports both Linux® and real-time applications, along with a comprehensive array of peripherals and 95K low-power, high-performance FPGA logic elements. With its full range of features and affordability, this kit enables swift testing of application concepts, firmware application development, as well as programming and debugging of user code.
Apart from conventional sales channels, the PolarFire SoC Discovery Kits will be accessible through a pilot initiative within the Microchip Academic Program in the latter half of 2024. By providing the Discovery Kit at a discounted rate to universities, Microchip is guaranteeing that upcoming engineers have immediate access to cutting-edge technology. This strategy not only enriches the hands-on learning opportunities for students but also synchronizes academic studies with the most recent industry advancements. Microchip's academic program provides tools for educators, researchers, and students globally, aiding universities in integrating advanced technology into their curriculum.
The Discovery Kit is centered around the PolarFire MPFS095T SoC FPGA, featuring an embedded microprocessor subsystem that includes a quad-core, 64-bit CPU cluster based on the RISC-V Instruction Set Architecture (ISA). The extensive L2 memory subsystem is configurable for either performance or deterministic operation and supports an asymmetric multi-processing (AMP) mode. The board is equipped with support for Microchip’s Mi-V ecosystem, a mikroBUS™ expansion header for Click boards™, a 40-pin Raspberry Pi® connector, and a MIPI® video connector. Expansion boards can be managed through protocols like I2C and SPI. The kit includes an embedded FP5 programmer for FPGA fabric programming and debugging, as well as firmware application development.
What is PolarFire SoC FPGA?
PolarFire SoC FPGA represents Microchip's fifth-generation family of non-volatile FPGA devices, leveraging cutting-edge 28 nm non-volatile process technology. These cost-optimized FPGAs are engineered to provide the lowest power consumption within mid-range densities. By integrating the industry's most power-efficient FPGA fabric, a 12.7 Gbps transceiver lane with the lowest power consumption, built-in low-power dual PCI Express Gen2 (EP/RP), and, in specific data security (S) devices, an integrated low-power crypto co-processor, PolarFire FPGAs effectively reduce the overall cost of mid-range FPGAs.
PolarFire FPGAs support operation at both 1.0 V and 1.05 V, allowing end-users to make trade-offs between power consumption and performance to align with the specific requirements of their applications. This document outlines the features of the production PolarFire FPGA, covering extended commercial (0 °C to 100 °C) and industrial (–40 °C to 100 °C) device offerings. Additionally, it includes details about the device offerings tailored for military temperate (–55 °C to 125 °C) grade devices.
Non-Volatile FPGA Fabric
The non-volatile FPGA fabric is constructed using advanced 28 nm low-power non-volatile process technology. Comprising distinct building blocks, the PolarFire FPGA fabric is delineated as follows:
Logic Element
On-chip Memory (LSRAM, μSRAM, sNVM, and μPROM)
Math Block
The configuration cells for FPGA fabric are Single Event Upset (SEU) immune, facilitating the configuration of I/Os and other aspects of the device. Unlike SRAM FPGAs, non-volatile FPGAs eliminate the need for a configuration process, powering up rapidly like an Application-Specific Integrated Circuit (ASIC) with minimal inrush current. This makes them ideal for root-of-trust first-up functionality in any system.
Logic Element
The 4-input Look-Up Table (LUT) within the logic element can be configured to implement a 4-input combinatorial function or an arithmetic function where the LUT output is XORed with a carry input to generate the sum output. Key features of the logic element include:
A fully permutable 4-input LUT optimized for the lowest power
A dedicated carry chain based on carry look-ahead technique
A separate flip-flop usable independently from the LUT
On-Chip Memory
PolarFire FPGAs incorporate four memory types, allowing designers to optimize for power, functionality, and area. Two are volatile memories:
LSRAM
μSRAM
LSRAMs are 20 Kbit SRAMs with built-in Single Error Correction Double Error Detection (SECDED) and interleaving to prevent multi-bit upsets (MBUs). μSRAMs are small distributed 64 x 12 RAMs, suitable for efficient implementation of small buffers, leaving LSRAM for wider and deeper memories. Non-volatile memories (NVMs) include:
μPROM
sNVM
μPROM, made of SEU-immune FPGA configuration non-volatile cells, is readable at runtime and writable during device programming. sNVM, accessible through system service calls, is readable and writable by the designer's application during runtime. It is an ideal storage location for boot code for soft processors and user keys.
LSRAM
Each LSRAM block consists of 20,480 bits of RAM and supports dual-port and two-port modes. LSRAM configurator in the Libero SoC PolarFire toolset enables automated combining and cascading of several LSRAM blocks into larger memories. LSRAM features include:
Operation at 428 MHz
True dual-port memory
Two-port memory (one dedicated write port and one dedicated read port)
• Data widths of ×1, ×2, ×5, ×10, ×20, ×40, and ×33 with SECDED enabled
• Multi-bit-upset mitigation
• Synchronous operation
• Independent port clocks
• Byte enables
• Registered inputs
• Output registers with separate enables and synchronous resets
• Read enables to conserve power while retaining output data
• Power switch to minimize static power when the LSRAM is not used
• Fast zeroization mode
Math Block
The fundamental unit in digital signal processing algorithms is the multiply-accumulate (MACC) operation, and PolarFire FPGAs incorporate a specialized 18 x 18 MACC block to efficiently implement low-power complex DSP algorithms. This includes applications such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast Fourier transform (FFT) for filtering and image processing. Adjacent logic elements near the math block allow the construction of an optional 16-word coefficient ROM.
Key features of the math block functionality include:
Operation at 500 MHz
An 18 × 18 two's complement multiplier accumulator with a 48-bit output width
Power-saving pre-adder designed to optimize linear phase FIR filter applications and minimize math block usage
Optional pipelining and dedicated buses for cascading
Dot-product mode specifically for complex multiplies
Please check out all of polar fire soc options in our website to find what you need and contact GUOYUAN ELECTRONICS for more imformation.
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